1. Field of the Invention
The present invention relates to a method for forming a three-dimensional metal-insulator-metal capacitive structure in an interconnection stack, and to the resulting structure.
2. Discussion of the Related Art
Conventionally, to provide integrated circuit chips, electronic components are formed at the surface of a semiconductor substrate. To connect the electronic components to one another, a stack of interconnection levels comprising metal tracks and vias surrounded with a dielectric material is formed above the substrate. Each level of the interconnection stack conventionally comprises a first stage in which are formed metal vias (called “via level” hereafter) and a second stage in which are formed metal tracks (called “metal level” hereafter).
The direct integration of capacitive metal-insulator-metal structures (better known as MIMs) in certain portions of the interconnection levels is known. FIG. 1 illustrates an example of such a structure as described, for example, in “High performance 3D damascene MIM capacitors integrated in copper back-end technologies” by S. Cremer, C. Richard, D. Benoit, C. Besset, J. R. Manceau, A. Farcy, C. Perrot, N. Segura, M. Marin, S. Becu, S. Boret, M. Thomas, S. Guillaumet, A. Bonnard, P. Delpech, S. Bruyere, published in 2006 Bipolar/BiCMOS Circuits and Technology Meeting (IEEE Cat No. 06CH37813), 2006.
FIG. 1 partially shows three interconnection levels Ln−1, Ln, and Ln+1, each level comprising a via level, respectively Vn−1, Vn, and Vn+1, and a metal level, respectively Mn−1, Mn, and Mn+1.
Metal tracks 10 are formed in each of metal levels Mn−1, Mn, and Mn+1. Metal tracks 10 are, for example, made of copper or of aluminum. In each of via levels Vn−1, Vn, and Vn+1 are provided conductive vias 12 enabling to connect metal tracks 10 of adjacent interconnection levels to one another. A dielectric material 14 surrounds the conductive regions of the interconnection stack and insulates these regions from one another. An insulating layer 16 is provided at the surface of each of metal levels Mn−1, Mn, and Mn+1 and of via levels Vn−1, Vn, and Vn+1. Layer 16, generally made to of silicon nitride, aims at avoiding the diffusion of the metal from a metal or via level to adjacent levels.
In the example of FIG. 1, a capacitive structure CV is provided in via level Vn. Capacitive structure CV is formed above a metal track 10 of metal level Mn−1, in a trench made in dielectric material 14 of via level Vn. Capacitive structure CV comprises a first conductive layer 18 forming a first electrode which extends on the walls and the bottom of the trench, in contact with track 10. At the surface of first electrode 18 is formed a stack of a layer of a dielectric material 20 and of a second conductive layer 22 forming the second electrode of the capacitive structure. The rest of the trench is filled with a conductive material.
To take a contact on first electrode 18, vias are provided in via level Vn above metal track 10 of metal level Mn−1. To form a contact with second electrode 22, a metal track portion is provided, in metal level Mn, above conductive region 24. A via is provided in via level Vn+1, above this track portion.
To obtain the structure of FIG. 1, additional steps with respect to conventional methods for forming an interconnection stack are necessary. Indeed, capacitive structure CV is formed in via level Vn before forming metal level Mn and the tracks and vias of interconnection level Ln. Further, in a structure such as that in FIG. 1, the series resistance associated with the capacitor is large and limits the high-frequency performance of the component.
Indeed, capacitor CV is formed by the placing in parallel of a “horizontal” capacitor, in the bottom of the trench formed in via level Vn, and of a “vertical” capacitor, formed at the level of the trench walls. The small thickness of conductive layer 18 implies a significant access resistance at the level of the walls of the capacitive structure, which limits cut-off frequency Fc of the component, defining the limit of the use of the component as a capacitor (as a first approximation, Fc=π*R*C/2, where R is the series resistance of the component and C its capacitance).
The component is thus only advantageous at low frequency.
Further, in a structure such as that in FIG. 1, metallization Mn cannot be used above capacitive structure CV. Indeed, to avoid forming short-circuits, the metal tracks located above conductive region 24 can only actually play the role of access vias and cannot be directly connected to other tracks of the same level. Thus, the surface above the capacitive structure cannot be used to form other conductive tracks. Two interconnection levels Ln and Ln−1 are thus necessary to form capacitive structure CV.
The forming of three-dimensional capacitive structures such as capacitive structure CV over the entire thickness of an interconnection level is also known. However, to obtain such a structure, relatively complex methods may be needed.
There thus is a need for a method for forming capacitive metal-insulator-metal structures in the interconnection stack of an integrated circuit, which overcomes all or part of the above-mentioned disadvantages.